In accordance with high integration of a semiconductor device, a pattern of a wiring or a separation width, which is required in a manufacturing process, tends to be micronized. Such a micronized pattern is formed by forming a resist pattern using a photolithography technique, and etching various base films using the resist pattern as a mask pattern (see, e.g., Japanese Patent Laid-Open Publication No. 2014-56864).
The photolithography technique is important in order to form a mask pattern, and it is now requested that micronization before and after a slimming processing do not exceed a resolution limit of the photolithography technique. A method of using a one-dimensional (1D) layout is known as a method of forming a fine mask pattern that does not exceed such a resolution limit of the photolithography technique.
The method of using the 1D layout includes a cut step of cutting a line or a space in a line-and-space shape, in which lines and spaces are repeated at an unmagnified pitch, at an optional position using a cut pattern. A pattern including a plurality of opening or a plurality of light shielding portions is used as the cut pattern.